Power supply for an electronic pabx

ABSTRACT

A compact power supply characterized by low heat dissipation is provided. Phase control of main silicon controlled rectifiers is provided by cosine modified ramp and pedestal control. Overvoltage and overcurrent conditions are detected by SCRs and relay means which reduce the amplitude of control signals to the main SCRs thus turning off the output of the system to prevent damage.

United States Patent 11 1 Keough et al. 1 July 3, 1973 POWER SUPPLY FORAN ELECTRONIC [56] References Cited PABX UNITED STATES PATENTS [75]Inventors: Timothy James Keough, Woodridge; 3,305,763 2/1967 Kupferberget a1 321/18 X Charles James Kalensky, Chicago, 3,354,378 11/1967.lewett 321/ 14 both f 111 3,577,177 5/1971 Hewlett 323/24 x [73]Assignee: International Telephone and Primary Examiner james D. Tramme"gelYegraph Corporauon New York A ttorney-C. Cornell Remsen. Delbert P.Warner et al. [22] Filed: Mar. 24, 1972 21 Appl. No.: 237,973 1 ABSTRACTRelated us. Application Data compact power supply characterized by 10117heat dlS- sipation 15 provided. Phase control of main s1l1con con- [63]Commuanon of May 1970 trolled rectifiers is provided by cosine modifiedramp abandoned and pedestal control. Overvoltage and overcurrentconditions are detected by SCRs and relay means [52] Cl 317/16 317/31317/33 which reduce the amplitude of control signals to the 317/33321/14 323/24 main SCRs thus turning off the output of the system to[51] Int. Cl. H02h 3/38 prevent damage [58] Field of Search 321/14, 18;323/24;

317/33 YR, 33 SC, 31, 16 5 Claims, 6 Drawing Figures /4 /0 7 7 i6 /2 Z IFULL wave C'Z/RREA/T 5 mmscme mew-5m 3 ac. a M/i/A/ 50? 0/005 F/L TEA551/5/7/1/5 4 0/005 5fi/D6E RCT/F/f/i RELflY WWW mFWD M {/5 01 5?CZ/lF/FEA/f 6V6? van/ 7415 C/FCM my (wr /WY 77 ;"6 /G {E} ifC'Z PULSE 74c (1 TrWA/EFORME/i 427 M TWA/WW5? T l u T' FULL 1741/5 I 0/005 P5 0 272? I 1 5/7/04: 5 32 1 Q 26 f 1 VOL 7/766 1 D/V/Of? i I Z5) [V771, I

C05/A/5 MUD/F/ED fl/ PfDEJT/VLFflA IP 1/ E 0J7 771 451 (/0 1 20 1 1 1 .7v 1 1 ,jft "w t fi 1 Patented July 3, 1973 3 Sheets-Sheet l PatentedJuly 3, 1973 3 Sheets-Sheet This is a continuation of application Ser.No. 36,942, filed May 13, 1970, now abandoned.

The presentinvention relates to power supplies and particularly to powersupplies for electronic PABXs.

The prior art power supply systems for PABXs have involved the use oflarge transformers and massive rectifier circuits. Such systems havefunctioned well in the past, but have consumed much power, have taken uprelatively large amounts of space, have produced great quantities ofheat, have required large cabinets and have required the use of muchcooling equipment.

With modern PABX switching systems employing solid state equipment therequirements for electrical power have been reduced. In addition, solidstate components take up very little space and it is desirable to reducethe space requirements for power supplies proportionately.

It is an object therefore of the present invention to provide powersupplies which are compact. This is so that the power supplies will notrequire an inordinate amount of cabinet space when compared with thespace required for the switching system itself.

It is a further object of this invention to provide power supplies whichdissipate very little heat. In this way, it is possible to avoid loss ofpower in the form of heat as well as the loss of power required tooperate cooling equipment.

In addition to the foregoing objects, it is an object of the inventionto provide improvements in the power supply relating to protectionagainst overloads, protection from overvoltage and protection in theevent of a short circuit.

In order to accomplish the foregoing objects and others ancillarythereto, a power supply is provided in which two SCRs in a bridgecircuit are alternatively turned on by control signals to produce afull-wave rectified voltage from an ac source. The control signals areproduced from a second circuit which includes a second bridge circuitfunctioning as a full-wave rectifier energized by the same ac source.Signals from the rectifier in the second circuit are processed by zenerdiodes and the resulting modified signals are compared with systemoutput voltages in a differential amplifier to provide a differencevolgage. This difference voltage is used to establish a pedestal voltagein a unit junction transistor oscillator; The output of the rectifier isfed directly to the emitter timing circuit of the UJT oscillator to adda cosine wave (cosine ramp function) to the pedestal voltage. The outputpulses from the UJT are used to trigger two additional SCR gatesalternately. These additional SCR gates in turn provide firing voltagesfor the main SCRs.

The above mentioned and other features and objects of this invention andthe manner of obtaining them will become more apparent, and theinvention itself will be best understood by reference to the followingdescription of an embodiment of the invention taken in conjunction withthe accompanying drawings, in which:

FIG. 1 is a block diagram illustrating the overall system,

FIGS. 2a and 2b together form a schematic diagram showing an embodimentof the invention in detail,

FIG. 2 shows how FIGS. 2a and 2b should be combined, and

FIGS. 3 and 4 present waveforms of use in attaining an understanding ofthe invention.

GENERAL DESCRIPTION The EPABX power modules are basically regulated SCRphase-controlled DC power supplies which utilize cosine-modified rampand pedestal control. Although some specific differences in circuitryexist between various modules employed in the practice of the invention,the basic operation of each is the same.

In general, power modules according to the invention operate in thefollowing manner, referring to the block diagram in FIG. 1. A thyrectordiode THl is connected across the incoming AC line indicated at terminal2, to provide transient voltage protection for the powersemi-conductors. The AC voltage from 2 is then impressed across a fullwave SCR/diode bridge rectifier indicated by block 4. The bridge SCRs(main SCRs) are phase controlled by circuitry located within the dottedblock 6. The operation of this phase control circuitry will be discussedin the following paragraph. The output of the bridge is heavily filteredby a L-C network at 8. A Free Wheeling Diode (FWD) provides a fastreverse recovery time to overcome the L' dt effect of the filterinductance when the bridge SCRs are reverse biased. The output of thesupply is current overload protected by means of a current sensitiverelay indicated by block 10 and is over-voltage protected by a crowbarSCR type circuit, indicated by block 12.

The main SCRs in the input bridge 4 are phasecontrolled in the followingmanner. A separate A-C input on terminal 20 is impressed across atransformer T1 and a full-wave diode bridge at 22. The output of thebridge rectifier 22 is fed directly to resistors R1 and R2. The otherside of R2 is connected to the emitter timing circuit of a UJTrelaxation oscillator or Unit Junction Transistor relaxation oscillator24. This adds a cosine wave to the UJT emitter circuit and compensatesfor the sinusoidal supply voltage. The result is a linear transfercharacteristic for the entire regulator.

The resistor R1 acts as a dropping resistor for a zener regulator 26.The output of a zener reference 28 is connected to one input side of adifferential amplifier at 30. The other input side of the amplifier at30 is connected to the output of a proportional voltage divider 32. Theinput to the divider is taken from the D C Voltage Output terminal 50.

Under normal operating conditions, the value of the output D C voltagewill lie within a certain specified voltage range and the differentialvoltage (AE) between the zener reference and the voltage divider will benear zero, where AE VzVfl The output AE of the differential amplifier at31 supplies current to the pedestal network 24 and establishes theamplitude of the pedestal in relation to the peak point (trigger)voltage of a unit junction transistor UJT. Superimposed on this pedestalis the cosine-modified ramp voltage. The PRF of the UJT trigger circuitis present by the choice of components in the timing circuit, voltagedivider, differential amplifier and zener reference. Changes in AE(error voltage) raise and lower the pedestal voltage depending on thepolarity of Vfb with respect to the zener reference (Vz). This in turnincreases or decreases the period of the UJT relaxation oscillator. TheUJT output pulse is synchronized to the AC input line by virtue of itsfull wave sinusoidal supply voltage.

The output pulse from the UJT trigger circuit is coupled through a pulsetransformer at 34 to the SCR Gating Circuits at 36. Since the Main SCRslocated in the Full Wave SCR/Diode Bridge 4 operate into a high reactiveload, the additional SCR circuit at 36 operating into a resistive loadwith zener voltage limiting is employed to trigger the gates of the mainSCRs. In this way dv/dt firing problems are avoided.

The two Main SCRs in the bridge rectifier 4 are each triggered onalternate cycles of the input AC waveform at a firing anglepredetermined by the UJT trigger circuits 24 and the DifferentialAmplifier 30.

In the event that the output DC Voltage of the power module shouldincrease or decrease this will result in a corresponding change infeedback voltage (Vjb) to the Differential Amplifier. The error voltage(AE) will change accordingly and the period of the UJT will increase ordecrease; retarding or advancing the firing angle of the Main SCRs. Thisof course will result in a corresponding increase or decrease in outputvoltage. When the output is within specifications, the error voltage(AE) will again be near zero and the firing angle for the Main SCR willcorrect for proper output voltage.

The slow starting capacitor C2 is employed to bring all the powermodules up to their rated voltages slowly and uniformly to allow forcapacitive loading effects. In the event of a current overload thecurrent sensitive relay in the current protect circuit closes and a SCRin the over-current circuit 14, is fired. The SCR illuminates a faultindicator lamp 16 and discharges the slow start capacitor. The triggerfrom the UJT gate circuit is inhibited and the conductor of the MainSCRs is decreased to a minimum. The output current decreases accordinglyand the current relay drops out. Now the slow start capacitor begins tore-charge and eventually reaches the voltage where the UJT circuit isallowed to operate. If the short circuit is still present, the entireprocess will be repeated. Each time this automatic reset feature occursthe fault indicator will flash, thereby localizing the fault to themodule level. The reset process is limited to a preset number ofoperations by circuitry external to the power modules.

Essentially the same process occurs when an overvoltage conditionexists. The output voltage is fed to the Overvoltage circuitry 18 and anSCR at 12 is fired if the voltage is too high. This SCR is crow-barredacross the D Cvoltage output of the supply and shortcircuits the outputwhen fired. This causes the current sensitive relay to close and theprocess discussed above occurs. The fault indicator 16' flashes asexplained above, thereby localizing the fault.

DETAILED DESCRIPTION Refer now to the schematic drawing in FIGS. 2a and2b for an exemplary power supply module in accordance with theinvention. The input A C voltage to'the full wave SCR/Diode bridge isstepped down to 16 VAC (rms) across terminals 2, 2 by the powertransformer TRl. The General Electric thyrector TI is placed across theA C input line to provide voltage transient protection for the supply.For a +5VDC supply the thyrector diode is rated at 25VAC (rms). Thethyrector will clip transient voltages at 150 to 200 percent of itsrated recurrent peak voltage.

The full-wave bridge 4 consists of two diodes and two Main SCRs. Theyare connected, in this example, for a positive voltage output. The MainSCRs are phase controlled by the circuitry associated with their gates.Initially it is assumed that the two Main SCRs Q1 and Q2 are notconducting (gates off) and produce no output voltage.

Assume that VAC from the power transformer TRl is connected viaterminals 20 and 20 across the full wave diode bridge MDl, MD2, MD3,MD4, so that a positive rectified full-wave, formed of segments of asine wave, occurs across the terminals 40, 42.

The output voltage of the full-wave diode bridge MDl, MD2, MD3, MD4 isconnected through a large resistor 5R2 to the timing capacitor 5C1 ofthe Unijunction Relaxation Oscillator. This capacitance causes a phaseshift in the sinusoidal supply voltage and produces a cosine waveform.

The output of the diode bridge is also connected to a dropping resistorR1. This resistance acts in conjunction with a 30V zener regulator diode26. The supply voltage to the Differential Amplifier formed usingtransistors Q3 and O4 is, therefore, a clipped sine wave of 30 volts 10percent amplitude. The resistor 3R4 and the 3.6 volt zener diode 28provide a reference voltage circuit for the differential amplifier. Thecathode of the zener 28 is connected to the base of Q3. The base of theother NPN transistor Q4 in the differential amplifier 30 is connected toa proportional D C voltage divider 32 formed by resistors 4R3, 4R4, 4R5.

A capacitor 4C1 is connected between the base and collector of Q4 tocancel ripple from the collector of Q4 which otherwise causes erraticfiring of the main SCRs Q1 and Q2. One side of the divider is connectedto the D C output of the supply at terminal 50 and the other side isconnected to ground. The potentiometer 4R4 in the divider is adjusted toprovide +5VDC at the supply output into a nominal load. When this occursthe voltage at the collector of the output transistor Q4 is divided bythe resistor network 5R4, SR3. This network of 5R4, 5R3 provides apedestal voltage across the capacitor 5C1 as it is charged through theseries diode 5Dl. To this pedestal voltage the previously mentionedcosine wave on capacitor 5C1 is added over the resistor 5R1 to producethe waveform shown in FIG. 3. Note that the R-C Time Constant of thepedestal is much less-than that of the cosine ramp path. The pedestal,therefore, is established rapidly and the ramp increases very slowly. Inother words the dv/dt of the ramp is much less than that of thepedestal.

The UJT relaxation oscillator supply voltage (Ebb) is approximately+20VDC in amplitude and is a modified sine wave. The result of using acosine modified ramp and a sinusoidal supply voltage for all the supplymodules is a linear output voltage transfer characteristic. That is, theD C output voltage changes linearly with respect to pedestal voltagechanges.

Since the supply voltage of the UJT is sinusoidal, the relaxationoscillator is reset every half cycle when the sinusoidal voltage goes tozero. In this manner the trigger pulses from the. oscillator to the SCRgates are synchronized to the A C line voltage. Note also that the UJTtriggers several times during one half cycle. However, only the firsttrigger should gate the SCRs. When the cosine ramp reaches the triggervoltage of the UJT, it turns on and a positive pulse occurs at Base 1.This pulse is coupled by means of a lzl :1 pulse transformer T2 to thegate circuits of the SCRs Q6 and Q7. Between Q6 and Q7, the SCR having apositive anode will fire. The resistor divider network 6R1, 6R2, 6R3 and7R1,

7R2, 7R3 on each SCR gate assures that proper gate current (i and gatevoltage. (V for SCR firing is furnished to the gates and that the gatedissipation rating is not exceeded.

Firing one of the gate circuit SCRs results in a positive modified sinewave of approximately 18 volts peak amplitude appearing at its cathode.The conduction angle of the modified sine wave is determined by therelationship between the UJT output trigger and the start of thetransformer secondary voltage wave form.

The time between the start of the secondary voltage and the trigger isdetermined by the intrinsic ratio of the UJT, the UJT supply voltageamplitude, the amplitude of the pedestal, the rate of change of thecosine ramp and the RC charging rate of a timing capacitor. When allthese factors are correct and the input A C is l6VAC and the outputvoltage is +5VDC the conduction angle of the SCR should be approximately90.

The cathode voltage of the gate scr is clipped by a 5.6V Zener Z6 or Z7to insure that the maximum forward gate voltage (V and maximum gatecurrent (I are not exceeded. This prevents excessive gate dissipation inthe gate circuits of the main SCRs Q1 and Q2. The two gate SCRs Q6 andQ7 fire in an alternate manner. Therefore, the main SCRs fire onalternate half-cycle of the input A C waveform. This results in modifiedfull wave rectification as shown in FIG. 4. The conduction angle of theoutput of the bridge is approximately 180. The peak output amplitude ofthe bridge output is approximately volts when typical forward drop ofthe semiconductors is considered.

The large inductor 1L1 (5 millihenries) which follows the bridge tendsto maintain a holding current through the SCR Q9 when the line voltagegoes to zero, preventing commutation. The Free Wheeling Diode 1D2provides a by-pass for this current. The reverse recovery time of 1D2 isvery fast to overcome the Ldi/dt effect of the inductor.

SHORT CIRCUIT PROTECTION The output of the Main bridge is heavilyfiltered by 1L1, 1C1 and 1C2 to reduce A C ripple. The filter includes acurrent sensitive relay CSR whose pull-in current is amperes. In theevent of a short circuit, the contacts of the relay are closed and sendthe +3OV zener clipped sine wave supply to the 180 ohms and 18 ohmsvoltage dividers 8R1, 8R2 in the gate circuit of the current overloadSCR Q8. The divider provides the proper gate voltage and current to firethe SCR Q8. When this occurs current flows throughthe indicator lamp l6and it illuminates. Even more important is the fact that current flowingfrom the Differential Amplifier to the pedestal network is divertedthrough the SCR. This decreases the pedestal to a minimum amplitude ofapproximately 4 volts which corresponds to the voltage drops acrossthree diodes and an SCR. This inhibits the trigger pulse from therelaxation oscillator and prevents the firing of the Main SCRs. The slowStart Capacitor C2 which is located external to and is common with anumber of individual power sources is discharged through the overcurrentSCR, Q8, when it fires. This turns off the power source by pulling downthe pedestal voltages and preventing the Main SCRs from triggering. Thefailure lamp 16 is illuminated to indicate the failure.

When the Main SCRs commutate, the output source voltage and current dropto zero. The current sensitive relay drops out and its contacts open.This removes the gate drive to the overcurrent SCR, Q8, and itcommutates. The fault light extinguishes and the slow start capacitor C2begins to charge through the diode path provided in each power source.It continues to charge until the diode is back biased. Then theDifferential Amplifier output re-establishes the pedestal after theproper delay time determined by the pedestal and cosine ramp, the UJTfires and triggers the gate SCRs Q6, Q7 which trigger the Main SCRs.

If the short condition has been removed, the supplies will continue tooperate in their normal manner. If the short is still present thecontacts of thevcurrent relay will close, the overcurrent SCR (Q8) willfire and the whole procedure repeats again.

OVERVOLTAGE PROTECTION The overvoltage protection circuit operates inthe following manner. Under normal voltage, the D C output voltage whichis fed back to the crow-bar SCR gate circuit 10L1, 10Zl, 10R4, MCI isnot sufficient to turn on the zener diode. Therefore, no gate voltage orcurrent is provided to the crow-bar SCR gate and it remains off. Whenthe D C output voltage rises out of specification sufficiently enough tobreak down the zener, a gate voltage and current are supplied to thecrow-bar SCR Q9. The SCR fires and acts as a short on the output of thepower supply. Excessive current is drawn through the current sensitiverelay CSR and its contacts close. This fires the overcurrent SCR (Q8) asexplained above. The cycle described above for overcurrent begins againand repeats. The only difference between the occurrences for overcurrentand overvoltage is that on each reset period the crow-bar SCR will fireand pull in the current sensitive relay for overvoltage conditions. TheSCR crow-bar does not fire for overcurrent conditions and only thecurrent relay is pulled in. The choke 10L1 and the capacitors 9C1 and10C1 in the crow-bar SCR gate circuit are used for transient protection.

The current delivering capability of the power sources is limited by thecurrent rating of the filter choke 1L1. For a +5VDC supply, the choke israted at 22.5 amps, the current sensitive relay is rated 25 amps and therated output current (full load) for the supply is 20 amps.

While the principles of the invention have been described above inconnection with specific apparatus and application, it is to beunderstood that this description is made only by way of example and notas a limitation on the scope of the invention.

We claim:

1. A power supply for an electronic system comprismg two main SCRsconnected in adjacent arms of a first bridge circuit responsive to an ACpower supply voltage and to control voltages to provide a desired DCoutput voltage,

a second bridge circuit coupled to receive a voltage proportional tosaid AC power supply voltage and provide a pulsating DC voltage,

means coupling said pulsating DC voltage to a capacitor to produce acosine ramp voltage across said capacitor,

a source of reference voltage,

a differential amplifier coupled to compare the reference voltage withthe DC output voltage of the system and to provide a difference voltagein accordance with the difference,

means for receiving said difference voltage and providing a pedestalvoltage proportional thereto, means for receiving said cosine rampvoltage and said pedestal voltage and forming an intermediate voltageproportional to the sum of said voltages, and two gate SCRs coupled tobe energized alternately by the intermediate voltage, said two gate SCRsdirectly providing separate control voltages to energize respective mainSCRs in adjacent arms of the second bridge circuit.

2. A power supply as claimed in claim 1, in which the second bridgecircuit forms a full-wave rectifier for providing said pulsating DCvoltages, and

the reference voltage is provided by a zener diode placed across saidpulsating DC voltage.

3. A power supply as claimed in claim 1, in which the second bridgecircuit forms a full-wave rectifier for providing said pulsating DCvoltages and the means for forming an intermediate voltage includes aunit junction transistor.

4. A power supply as claimed in claim 1, in which means are provided forprotecting the power supply against excessive current levels,

said means including a current sensitive relay responsive to currentabove a certain level to close contacts and energize a current overloadSCR,

said current overload SCR including connections to reduce the pedestalvoltage, and thus lower the intermediate voltage and the control signalsbelow levels necessary to turn on the two SCRs in the second bridge.

5. A power supply as claimed in claim 4, in which means are provided forprotecting the system from an overvoltage,

said means including a zener diode and a SCR connected across outputterminals of the system,

said zener diode responding to overvoltage to conduct,

means coupling the zener diode to control the SCR across the output toproduce a short circuit through the SCR when the zener conducts,

said short circuit causing operation of said means for protectingagainst excessive current levels

1. A power supply for an electronic system comprising two main SCRsconnected in adjacent arms of a first bridge circuit responsive to an ACpower supply voltage and to control voltages to provide a desired DCoutput voltage, a second bridge circuit coupled to receive a voltageproportional to said AC power supply voltage and provide a pulsating DCvoltage, means coupling said pulsating DC voltage to a capacitor toproduce a cosine ramp voltage across said capacitor, a source ofreference voltage, a differential amplifier coupled to compare thereference voltage with the DC output voltage of the system and toprovide a difference voltage in accordance with the difference, meansfor receiving said difference voltage and providing a pedestal voltageproportional thereto, means for receiving said cosine ramp voltage andsaid pedestal voltage and forming an intermediate voltage proportionalto the sum of said voltages, and two gate SCRs coupled to be energizedalternately by the intermediate voltage, said two gate SCRs directlyproviding separate control voltages to energize respective main SCRs inadjacent arms of the second bridge circuit.
 2. A power supply as claimedin claim 1, in which the second bridge circuit forms a full-waverectifier for providing said pulsating DC voltages, and the referencevoltage is provided by a zener diode placed across said pulsating DCvoltage.
 3. A power supply as claimed in claim 1, in which the secondbridge circuit forms a full-wave rectifier for providing said pulsatingDC voltages and the means for forming an intermediate voltage includes aunit junction transistor.
 4. A power supply as claimed in claim 1, inwhich means are provided for protecting the power supply againstexcessive current levels, said means including a current sensitive relayresponsive to current above a certain level to close contacts andenergize a current overload SCR, said current overload SCR includingconnections to reduce the pedestal voltage, and thus lower theintermediate voltage and the control signals below levels necessary toturn on the two SCRs in the second bridge.
 5. A power supply as claimedin claim 4, in which means are provided for protecting the system froman overvoltage, said means including a zener diode and a SCR connectedacross output terminals of the system, said zener diode responding toovervoltage to conduct, means coupling the zener diode to control theSCR across the output to produce a short circuit through the SCR whenthe zener conducts, said short circuit causing operation of said meansfor protecting against excessive current levels.